diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index 1d3fc1a..a06ef7b 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -330,29 +330,26 @@
 	struct rk3036_pll *pll = &priv->cru->pll[1];
 
 	/* pll enter slow-mode */
-	rk_clrsetreg(&priv->cru->cru_mode_con,
-		     DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+	rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
 		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
 
 	/* use integer mode */
 	rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
 
 	rk_clrsetreg(&pll->con0,
-		     PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
+		     PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
 		     (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) |
 			dpll_init_cfg.fbdiv);
-	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
-			PLL_REFDIV_MASK << PLL_REFDIV_SHIFT,
-			(dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
-			 dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
+	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
+		     (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
+		      dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
 
 	/* waiting for pll lock */
 	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
 		rockchip_udelay(1);
 
 	/* PLL enter normal-mode */
-	rk_clrsetreg(&priv->cru->cru_mode_con,
-		     DPLL_MODE_MASK << DPLL_MODE_SHIFT,
+	rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK,
 		     DPLL_MODE_NORM << DPLL_MODE_SHIFT);
 }